As VLSI technology scales, interconnects are becoming the dominant factor determining system performance and power dissipation. Interconnect reliability due to electro-migration and electromagnetic interference compliance (EMC) are fast becoming serious design issues particularly for long signal lines. In fact, it has been recently shown that interconnect Joule heating in advanced technology nodes can strongly impact the magnitude of the maximum temperature of the global lines despite negligible changes in chip power density which will, in turn, strongly affect the electro-migration lifetime of the interconnect. In analog designs, uni-directional current flow and smaller wire geometries create EM concerns for the signal nets as well. The behavior of analog circuits is even more sensitive to layout induced parasitics and thus electro-migration problems due to the unidirectional current flows in various circuit components. Parasitics not only influence the circuit performance but may often render it non-functional.
In addition to the rising concerns about electro-migration, voltage drop, also called IR drop, represents another class of challenges for modern electronic circuits. Voltage drop represents the voltage reduction that occurs on power supply networks. The IR drop may be static or dynamic and results from the existence of non-ideal elements—the resistance within the power and ground supply wiring and the capacitance between them. While static voltage drop considers only the average currents, dynamic voltage drop considers current waveforms within clock cycles and has an RC transient behavior. Similar effects may be found in ground wiring, usually referred as ground bounce, whereby current flows back to the ground/VSS pins causing its voltage to fluctuate. Both effects contribute to lower operating voltages within devices (e.g., logic cells/gates in digital circuits), which in general increases the overall time response of a device and might cause operational failures due to heat dissipation.
Conventional steady-state or transient thermal analyses use time consuming time-stepping or domain discretization algorithms such as finite element methods or finite difference methods on discretized designs. Moreover, these conventional steady-state or transient thermal analyses are often after-the-fact in that these analyses are usually performed after electronic designs are completed at, for example, the block level, the chip level, the package level, or even the board level at which integrated circuit blocks are integrated with a printed circuit board. The limitations on the sizes of time-step and the amount of computation time as well as intensive computation have rendered transient thermal analyses less than desired. Moreover, conventional EMC analyses are often performed as separate analyses detached from the electronic design stage and the thermal analyses of the electronic designs.
Given the advantages provided by the thermal analyses, EMC analyses, and the electrical analyses, there exists a need for effective and efficient technique to implement schematic driven, unified thermal and electromagnetic interference compliance analyses for electronic circuit designs.